View MC33411B_319276.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Order this document by MC33411A/D
MC33411A/B 900 MHz Analog Cordless Phone Baseband with Compander
The MC33411 900 MHz Analog Cordless Phone Baseband system is designed to fit the requirements of a 900 MHz analog cordless telephone system. Included are three PLLs (Phase-Locked Loops). Two are intended for use with external VCOs and 64/65 or 128/129 dual modulus prescalers, and can control the transmit and receive (LO1) frequencies for 900 MHz communication. The third PLL is configured as the 2nd local oscillator (LO2), and is functional to 80 MHz. Also included are muting, audio gain adjust (internal and external), low battery/carrier detect, and a wide range for the PLL reference frequency. The power supply range is 2.7 to 5.5 V. "A" version devices have programmable MCU clock out and reference oscillator disable functions, whereas these functions are always enabled for "B" version devices.
900 MHz ANALOG CORDLESS PHONE BASEBAND WITH COMPANDER
SEMICONDUCTOR TECHNICAL DATA
* * * * * * * * * * * *
Complete Expander/Compressor for Superior Noise Rejection Two PLLs and a LO Suitable for a 900 MHz System Minimal External Components Transmit Path Includes Adjustable Gain Amplifier, Filters, Mute, Compressor with Bypass and Limiter Receive Path Contains Data Slicer, Adjustable Gain Amplifier, Sidetone Attenuator, Filters, Expander with Bypass, Mute, Volume Control and Power Amplifier Dual A/Ds are Provided to Monitor RSSI and VCC Independent Power Amplifier with Differential Outputs and Mute Selectable Frequency for Switched Capacitor Filters, PLLs and the LO Reference Frequency Source can be a Crystal or System Clock Serial P Port to Control Gain, Mute, Frequency Selection, Phase Detector Gain, Power Down Modes, Low Battery Detect and Others Power Supply Range: 2.7 to 5.5 V Power Down Modes for Power Conservation Simplified Block Diagram
DS In VCC RSSI Tx In Data Slicer Dual A/D Amp/Mute Compressor Filter Gain Adj Filter Sidetone Attn Mute Expander Power Amp MCU Interface Programmable Counters PLL #1 PLL #2 2nd LO
48
1
FTA SUFFIX PLASTIC PACKAGE CASE 932 (LQFP-48)
ORDERING INFORMATION
Device MC33411AFTA MC33411BFTA Operating Temperature TA = -20 to 70C Package LQFP-48
DS Out
Tx Out Audio In MCU Clock Clock Enable Data
Rx Out
Tank LO2 Out
This device contains 11,108 active transistors.
LPF+ VCO + Prescaler
LPF+ VCO + Prescaler
LPF
(c) Motorola, Inc. 1999
Rev 2
MOTOROLA RF/IF DEVICE DATA
1
MC33411A/B
Figure 1. Test Circuit
VCC 1.0 1.0 1.0 4.99 k 0.47 4.99 k 130 1.0 VCC 0.1
Tx Audio
1.0 0.1 VAG 26 47.5 k MCI 25 47.5 k
Rx
Out 36 E In 35 Ecap 34 E Out 33 PAI 32 Gnd PA PAO- 31 30 PAO+ 29
VCC PA 28
4.7 VB 27
Rx Mute 1.0 k RSSI In 1.0 Rx Audio In 38 1.0 DS In VCC 49.9 LO2 Out VCC 0.001 0.1 5.6 p LO2 Ctl 44 2nd LO VCO LO2 VCC 1.0 LO2+ 41 39 BG Vref VCC Audio AALPF LPF 37
Expander
Vol Ctl
Power Amp Power Amp Mute Comp PT VB
Mic Amp 24 MCO VCC Audio 0.1 C In VCC 10 1.0
Exp PT Attn Rx Gain Adj
ALC SPI Compressor SPI Side Tone Attn Low Max Gain
23
22
Gnd Audio
RSSI 6b A/D Converter VCC 6b A/D Converter
SPI
40
21
VCC Ccap 0.47 1.0 C Out 1.0
SPI
20
42 Tx Gain Adj 43 Data Slicer Limiter LPF Tx Mute
19
Lim In Tx Out 1.0 DS Out Fref Out 0.1 10 k
18
17 Inverter SPI
LO2- 100 p 5.62 k LO2 Gnd
45
14b Ctr SCF Clk LO2 Phase Detect 7b A' 13b N' Divide By 2 6b SCF Clk Ctr
16
46
15
Fref In Gnd Digital
LO2PD LO2 Gnd
47
12b Ref Ctr 13b N 7b A MCU Interface MCU Clk Ctr SPI
14
48
13 MCU Clk Out
Mod Ctl
Rx Phase Detect
Tx Phase Detect
Mod Ctl
1
2 FRx MC FRx VCC 0.01 0.001
3 PLL VCC 1.0
4 Rx PD
5 PLL Gnd
6 Tx PD VCC
7 PLL VCC 1.0
8 FTx
9
10 FTx MC EN
11 CLK
12 Data
0.001
0.01 49.9
RF In
49.9
RF In
2
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
MAXIMUM RATINGS
Rating Power Supply Voltage Junction Temperature Maximum Power Dissipation Symbol VCC TJ PD Value -0.5 to 6.0 -6.5 to 150 150 Unit V C mW
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Recommended Operating Conditions, Electrical Characteristics tables or Pin Descriptions section. 2. Meets Human Body Model (HBM) 2000 V and Machine Model (MM) 200 V. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Characteristic Supply Voltage Operating Ambient Temperature Input Voltage Low (Data, CLK, EN) Input Voltage High (Data, CLK, EN) Frequency Range (Fref in) Bandgap Reference Voltage Symbol VCC TA Vil Vih Frange VB Min 2.7 -20 - Tx PLL VCC - 0.3 4.0 - Typ 3.6 - - - - 1.5 Max 5.5 70 0.3 - 18.25 - Unit Vdc C V V MHz V
DC ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, TA = 25C, unless otherwise noted.)
Characteristic Static Current Active Mode (R5/8 to 0 = 0; R6/7 = 0) Receive Mode (R5/8, 7, 3, 2, 0 = 0; R6/7 = 0; R5/6,5,4,1 = 1) Standby Mode (R5/0 = 0; R6/7 = 0; R5/8 to 1 = 1) Inactive Mode, A only (R5/8 to 0 =1; R6/7 = 1) Data Slicer Only RSSI/Batt A/D Only Tx Audio Only Rx Audio Only PA Only 2nd LO/Fref Only Rx PLL/Fref Only Tx PLL/Fref Only Ref Osc Only, "A" version only Reference Voltage, Unadjusted Symbol ACT ICC Rx ICC STD ICC INA ICC DS ICC AD ICC TxA ICC RxA ICC PA ICC 2LO ICC RxPLL ICC TxPLL ICC ROSC ICC VB Min - - - - - - - - - - - - - 1.38 Typ 15 10 500 10 100 70 1.4 1.4 1.0 6.0 1.0 1.0 500 1.5 Max 20 13 1500 15 - - - - - - - - - 1.62 Unit mA mA A A A A mA mA mA mA mA mA A V
ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.) Characteristics Rx AUDIO PATH Absolute Gain (Vin = -20 dBV) Gain Tracking (Referenced to Eout for Vin = -20 dBV) Vin = -30 dBV Vin = -40 dBV Total Harmonic Distortion (Vin = -20 dBV) Maximum Input Voltage (VCC = 2.7 V) Maximum Output Voltage (Increase input voltage until output voltage THD = 5%, then measure output voltage) Rx Audio In E In E Out E Out G Gt -21 -42 Rx Audio In Rx Audio In E In E Out VOmax PAO- THD - - -2.0 -20 -40 0.7 -11.5 0 -19 -38 1.0 - - % dBV dBV -4.0 0 4.0 dB dB Input Pin Measure Pin Symbol Min Typ Max Unit
NOTES: 1. Values specified are pure numbers to the base 10. 2. Typical performance parameters indicate the potential of the device under ideal operating conditions.
MOTOROLA RF/IF DEVICE DATA
3
MC33411A/B
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.) Characteristics Rx AUDIO PATH (continued) Input Impedance RxAudio In E In Attack Time Ecap = 0.5 F, Rfilt = 40 k Release Time Ecap = 0.5 F, Rfilt = 40 k Compressor to Expander Crosstalk (Vin = -10 dBV, VE In = AC Gnd) Rx Muting (Vin = -20 dBV, Rx Gain Adj = 01111) Rx High Frequency Corner (Vin = -20 dBV) SCF Counter = 31d Low Pass Filter Passband Ripple (Vin = -20 dBV) Rx Gain Adjust Range Rx Gain Adjust Steps Audio Path Noise, C-Message Weighting (Vin = AC Gnd) E In E In MCI Rx Audio In Rx Audio In Rx Audio In Rx Audio In Rx Audio In Rx Audio In Rx Out E Out PA Out Volume Control Adjust Range Volume Control Levels Side Tone Attenuate Selections Side Tone Attenuate (Referenced to E In) Selection = 00 Selection = 01 Selection = 10 Selection = 11 Side Tone Attenuate Threshold (C Out/E In) Output Swing, 5.0 mA load (VPAO+ @ -5.0 mA - VPAO+@ 5.0 mA) Output Swing, 5.0 mA load (VPAO- @ -5.0 mA - VPAO-@ 5.0 mA) Output Swing, No Load Output Swing, No Load Maximum Output Current Power Amp Mute (Vin = -20 dBV, RL = 130 ) PAI Rx Audio In E In Rx Audio In E Out E Out Rx Out E Out VCtlRange Vcn STAn STA - - - - STAthr - 0.0 1.5 3.0 5.2 -3.0 - - - - - dB E Out E Out E Out E Out Rx Out Rx Out Rx Out Rx Out ta tr CT Me Rx fch Ripple Rx Range Rx n EN - - - - - - -85 <-95 <-95 -14 to 16 16 4 - - - - - - dB dB Zin - - - - - - 3.6 - - - 600 7.5 3.0 13.5 -90 -84 3.8 0.4 -9.0 to 10 20 - - - - -60 -60 4.0 0.6 - - dBV mS mS dB dB kHz dB dB k Input Pin Measure Pin Symbol Min Typ Max Unit
POWER AMP/MUTE (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode, fin = 1.0 kHz) PAI PAI PAI PAI PAO+ PAO- PAO+ PAO- PAO-, PAO+ PAO- VOmax VOmax VOmax VOmax IOmax Msp 1.3 1.3 - - - - 2.4 2.4 2.7 2.7 5.0 -92 - - - - - -60 Vpp Vpp Vpp Vpp mA dB
MIC AMP (VCC = 3.6 V, TA = 25C, Active Mode, fin = 1.0 kHz) Open Loop Gain MCI Gain Bandwidth Maximum Output Swing (RL = 10 k) MCI MCI
MCO MCO MCO
AVOL GBW VOmax
- - -
100.000 100 3.2
- - -
V/V kHz Vpp
NOTES: 1. Values specified are pure numbers to the base 10. 2. Typical performance parameters indicate the potential of the device under ideal operating conditions.
4
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.) Characteristics Input Pin Measure Pin Symbol Min Typ Max Unit
Tx AUDIO PATH (VCC = 3.6 V, Limiter, Mutes, ALC disabled, TA = 25C, Gain = 1, Active Mode, fin = 1.0 kHz) Absolute Gain (Vin = -10 dBV) MCI TX Out G -4.0 0 Gain Tracking (Referenced to Tx Out for Vin = -10 dBV) Vin = -30 dBV Vin = -40 dBV Total Harmonic Distortion (Vin = -10 dBV) Maximum Output Voltage (Increase input voltage until output voltage THD = 5%, then measure output voltage. Tx Gain Adj = 8.0 dB) Input Impedance Attack Time Ccap = 0.5 F, Rfilt = 40 k Release Time Ccap = 0.5 F, Rfilt = 40 k Expander to Compressor Crosstalk (Vin = -20 dBV, PA no load, VCin = AC Gnd) Tx Muting (Vin = -10 dBV) ALC Output Level (When Enabled) Vin = -10 dBV Vin = -2.5 dBV ALC Slope (When Enabled) Vin = -10 dBV Vin = -2.5 dBV ALC Input Dynamic Range Limiter Output Level (When Enabled, Vin = -2.5 dBV) Tx High Frequency Corner (Vin = -10 dBV, Unity Gain) SCF Counter = 31d Low Pass Filter Passband Ripple (Vin = -10 dBV) MCU Clock or SCF Spurs (Vin = -10 dBv, relative to SCF or MCU Fundamental) Maximum Compressor Gain (Vin = -70 dBV) R6/8 = 0 R6/8 = 1 Tx Gain Adjust Range Tx Gain Adjust Steps C In C In E In MCI MCI MCI Tx Out Gt -11 -17 MCI MCI Tx Out Tx Out THD VOmax - -8.0 -10 -15 0.5 -5.0
4.0
dB dB
-9.0 -13 1.2 - % dBV
C In Tx Out Tx Out Tx Out Tx Out Tx Out
Zin ta tr CT Mc ALCout
- - - - - -15 -13
10 3.0 13.5 -60 -88 -13 -11 0.25
- - - -40 -60 -8.0 -6.0 0.4
k mS mS dB dB dBV
MCI
Tx Out
Slope
0.1
dB/dB
C In Lim In Lim In Lim In Lim In MCI
Tx Out Tx Out Tx Out Tx Out Tx Out Tx Out
DR Vlim Tx fch Ripple - AVmax
- -10 3.45 - -
-16 to -2.5 -7.0 3.65 0.4 -25
- - 3.85 1.0 -
dBV dBV kHz dB dBc dB
- - Lim In Lim In Tx Out Tx Out Tx Range Tx N - -
21 12 -9.0 to 10 20
- - - - dB
DATA AMP COMPARATOR (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active or Receive Mode) Hysteresis Threshold Voltage Input Impedance Output Impedance Output High Voltage (Vin = VCC - 1.0 V, Ioh = 0 mA) DS In DS In DS In DS Out DS Out DS In DS Out DS Out Hys VT Zin Zout Voh 20 - 200 - VCC Audio - 0.1 - - 42 VCC - 0.7 250 100 VCC Audio 0.1 10 60 - 280 - - mV V k k V
Output Low Voltage (Vin = VCC - 0.4 V, Iol = 0 mA) Maximum Frequency
DS In DS In
DS Out DS Out
Vol Fmax
0.4 -
V kHz
NOTES: 1. Values specified are pure numbers to the base 10. 2. Typical performance parameters indicate the potential of the device under ideal operating conditions.
MOTOROLA RF/IF DEVICE DATA
5
MC33411A/B
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.) Characteristics Input Pin Measure Pin Symbol Min Typ Max Unit
RSSI/LOW BATTERY A/D (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active or Receive Mode) RSSI Voltage Range Minimum (R5/17-12 = 0) Interim (R5/17-12 = 100000) Maximum (R5/17-12 = 1) Low Battery Detect Operating Range Minimum Interim (R5/23-18 = 101111) Maximum (R5/23-18 = 1) Differential Non-linearity Resolution Input Current RSSI In/ VCC Audio RSSI In/ VCC Audio SPI SPI RSSI In A/D DNL Resolution Iin VCC Audio SPI LOWB Range - 2.7 - -1.0 - -80 2.7 - 3.75 0.5 6 20 - 3.1 - 1.0 - 80 LSB Bits nA A A mVpp RSSI In SPI RSSI Range - .744 - 0 - 1.6 - .792 - V V
REFERENCE FREQUENCY (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode) Input Current High (Vin = VCC) Input Current Low (Vin = 0 V) Minimum Input Voltage Fref In Input Impedance Output Impedance Fref in Fref in Fref in Fref out Fref in Fref out Iih Iil Vin Zin Zout 2.0 -15 300 - - 5.0 -5.0 -
2.9 pF||11.6 k 2.5 pF||4.5 k
15 -2.0 - - -
MICROPROCESSOR INTERFACE (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active or Receive Mode) Input Low Voltage Input High Voltage Data/EN /CLK Data/EN /CLK Data, EN, CLK Data, EN, CLK Data, EN, CLK CLK Data, CLK, EN EN, CLK Data, CLK Data, CLK EN, CLK EN, CLK Vil Vih 0 Tx PLL VCC - 0.3 -5.0 - - 2.0 - - - - - - - Tx PLL VCC - 0.3 - - 0.3 Tx PLL VCC - 5.0 - - - - - - - - - - V V
Input Current Low (Vin = 0.3 V, Standby Mode) Data, EN, CLK Input Current High (Vin = 3.3 V, Standby Mode) Data, EN, CLK Hysteresis Voltage Data, EN, CLK Maximum Clock Frequency Input Capacitance Data, EN, CLK EN to CLK Setup Time Data to CLK Setup Time Hold Time Recovery Time Input Pulse Width MCU Interface Power-Up Delay Output High Voltage (Ioh = 0 mA)
Iil Iih Vhys Fmax Cin tsuEC tsuDC th trec tw tpuMCU
0.4 1.6 1.0 - 8.0 200 100 90 90 100 100 3.5
A A V MHz pF nS nS nS nS nS S V
MCU Clk Out
Voh
NOTES: 1. Values specified are pure numbers to the base 10. 2. Typical performance parameters indicate the potential of the device under ideal operating conditions.
6
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.) Characteristics Input Pin Measure Pin Symbol Min Typ Max Unit
MICROPROCESSOR INTERFACE (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active or Receive Mode) Output Low Voltage (Iol = 0 mA) Output High Voltage (Ioh = 0 mA) MCU Clk Out Data Vol Voh - Tx PLL VCC - 0.3 - 0.1 3.5 0.3 - V V
Output Low Voltage (Iol = 0 mA)
Data
Vol
0.1
0.3
V A
Rx/Tx PLL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active or Receive Mode) Output Source Current (VPD = 0.5 V or VCC - 0.5 V) 100 A mode 400 A mode Output Sink Current (VPD = 0.5 V or VCC - 0.5 V) 100 A mode 400 A mode Current Match, 100 A mode or 400 A mode, VPD = VCC / 2 (i.e., 100 x (ABS (Ioh / Iol ))) Output Off Current (VPD = VCC /2),100 A mode or 400 A mode Input Current Low (Vin = 0 V) Input Current High (Vin = VCC) Input Bias Voltage Output Voltage High (Ioh = 0 mA, Voltage Mode) Output Voltage High (Ioh = 0 mA, Voltage Mode) Output Voltage Low (Iol = 0 mA, Voltage Mode) Output Current High (Voh = 0.8 V, Current Mode) Output Current Low (Vol = 0.8 V, Current Mode) Maximum Input Frequency Input Voltage Swing Modulus Control Prop Delay FRx FTx Ioh Rx PD & Tx PD Iol Rx PD & Tx PD Rx PD Tx PD Rx PD Tx PD FRx FTx FRx FTx FRx FTx FRxMC FTxMC FRxMC FTxMC FRxMC FTxMC FRxMC FTxMC FRx FTx FRx FTx FRxMC FTxMC Match Ioz Iil Iih Vbias Voh Voh Vol Ioh Iol Fmax Vin - 70 280 80 -80 -10 - - - - - -130 70 20 200 - 100 400 100 5.0 -7.5 10 1.5 Rx PLL VCC - 0.1 Tx PLL VCC - 0.1 0.1 -100 100 - - 20 130 520 125 80 - 14 - - - - -70 130 - 1200 - % nA A A V V V V A A MHz mVpp nS -130 -520 -100 -400 -70 -280 A
LO2 PLL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode) Output Source Current (VPD = 0.5 V or VCC - 0.5 V) 100 A mode 400 A mode Output Sink Current (VPD = 0.5 V or VCC - 0.5 V) 100 A mode 400 A mode Current Match, 100 A mode or 400 A mode, VPD = VCC / 2 (i.e., 100 x (ABS (Ioh / Iol ))) LO2PD Ioh -130 -520 LO2PD Iol 70 280 LO2PD Match 80 100 400 100 130 520 125 % -100 -400 -70 -280 A A
NOTES: 1. Values specified are pure numbers to the base 10. 2. Typical performance parameters indicate the potential of the device under ideal operating conditions.
MOTOROLA RF/IF DEVICE DATA
7
MC33411A/B
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.) Characteristics Input Pin Measure Pin Symbol Min Typ Max Unit
LO2 PLL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode) Output Off Current (VPD = VCC /2) Input Current Low (Vin = 0.5 V) Input Current High (Vin = VCC - 0.5 V) Input Voltage Range Maximum 2nd LO Frequency LO2 Out Drive (25 load) COUNTERS (VCC = 3.6 V, VB = 1.5 V, TA = 25C, Active Mode) 12-Bit Reference Counter Range [Note 1] 13-Bit N Counter Range [Note 1] 7-Bit A Counter Range [Note 1] 64/65 Modulus Prescaler 128/129 Modulus Prescaler 14-Bit LO2 Counter Range [Note 1] 6-Bit Counters (for SCF) [Note 1]
NOTES: 1. Values specified are pure numbers to the base 10. 2. Typical performance parameters indicate the potential of the device under ideal operating conditions.
LO2PD LO2Ctl LO2Ctl LO2Ctl
Ioz Iil Iih Vrange
-80 -1.0 - 0.4 65
5.0 -0.02 0.02 - 80 180
80 - 1.0 VCC - 245
nA A A V MHz mVpp
Vout
112
- - - - - -
3 to 4095 3 to 8191 0 to 63 0 to 127 12 to 16383 3 to 63
- - - - - -
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PIN FUNCTION DESCRIPTION
Description Pin 1 Symbol/Type FRx MC (Output) Description
Rx PLL VCC 100 A
Modulus Control Output for the Rx PLL section. Can be set to output in current mode or voltage mode, selectable with bit 3/16.
Current Mode 1 FRx MC Rx PLL VCC 100 A
Voltage Mode
2
FRx (Input)
PLL VCC
Receives the signal from the external 64/65 or 128/129 prescaler. DC bias is at 1.3 V.
2 FRx
200 k
Bias 80 A
NOTE:
1. All VCC pins must be within 0.5 V of each other.
8
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PIN FUNCTION DESCRIPTION (continued)
Description Pin 3 Symbol/Type Rx PLL VCC (Input) Description
3 10 0.01 10 Rx PLL Section VCC
MC33411A/B
Supply pin for the Rx PLL section. Allowable range is 2.7 to 5.5 V and must be within 0.5 V of all other VCC pins. Good bypassing is required and isolation with a 10 resistor is recommended.
4
Rx PD (Output)
Rx PLL VCC 100/ 400 A Rx PLL VCC 100/ 400 A
125 4 125 to Filter Rx PD
Rx Phase Detector Output. The output either sources or sinks current, or neither, depending on the phase difference of the phase detector input signals. During lock, very narrow pulses with a frequency equal to the PLL reference frequency are present. Output current is either 100 A or 400 A, selectable with bit 2/20.
5 6 7
PLL Gnd Tx PD (Output) Tx PLL VCC (Input)
Tx PLL Section, MCU Serial Interface, Reference Oscillator
Ground pin for the PLL section. A direct connection to a ground plane is strongly recommended. Same as Pin 4, except powered from Tx PLL VCC. Tx Phase Detector Output. Description same as for Pin 4, except bit 1/20 controls the current level. Supply pin for the Tx PLL section, MCU Serial Interface, MCU Clock Counter, and the Reference Oscillator. Allowable range is 2.7 to 5.5 V and must be within 0.5 V of all other VCC pins. Good bypassing is required and isolation with a 10 resistor is recommended.
7
10
0.01
10
VCC
8 9
FTx (Input) FTx MC (Output)
Same as Pin 2.
Receives the signal from the external 64/65 or 128/129 prescaler. DC bias is at 1.5 V. Modulus Control Output for the Tx PLL section. Can be set to output in a current mode or a voltage mode, selectable with bit 3/16.
Tx PLL VCC 100 A Current Mode 9 FTx MC Tx PLL VCC 100 A
Voltage Mode
NOTE:
1. All VCC pins must be within 0.5 V of each other.
MOTOROLA RF/IF DEVICE DATA
9
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PIN FUNCTION DESCRIPTION (continued)
Description Pin 10 Symbol/Type EN (Input) Description
Tx PLL VCC
MC33411A/B
Enable Input for the MCU Interface section. Hysteresis threshold is within 0.5 V of ground and VCC. See text for proper waveform required at this pin.
10 Enable
240 1.0 A
11
CLK (Input)
Same as Pin 10.
Clock Input for the MCU Interface section. Hysteresis threshold is within 0.5 V of ground and VCC. Data is written or read out on clock's rising edge. Maximum clock rate is 2.0 MHz.
Tx PLL VCC
12
Data (I/O)
Data I/O line for the MCU Interface section. Both address and data are provided to/from this pin. Input threshold is within 0.5 V of ground and VCC. Data is written or read out on clock's rising edge.
12 Data
240 1.0 A Tx PLL VCC Disable Data
13
MCU Clk Out (Output)
Tx PLL VCC Tx PLL VCC
1.0 k
13 Clk Out
The microprocessor clock output is derived from the reference oscillator and a programmable divider with divide ratios of 2 to 312.5. It can be used to drive a microprocessor and thereby reduce the number of crystals required in the system design. The driver has an internal resistor in series with the output which can be combined with an external capacitor to form a low-pass filter to reduce radiated noise on the PCB. This output also functions as the output for the counter test modes. 1) For the MC33411A the Clk Out can be disabled via the MCU interface. 2) For the MC33411B this output is always active (on).
14
Gnd Digital
Ground for the Data, MCU Clk Out, and Fref Out digital Outputs. A direct connection to the ground plane is strongly recommended.
NOTE:
1. All VCC pins must be within 0.5 V of each other.
10
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PIN FUNCTION DESCRIPTION (continued)
Description Pin Symbol/Type Fref In, Fref Out Description 15, 16
Tx PLL VCC 100 Fref Out 16
MC33411A/B
Reference Frequency Input for various portions of the circuit, including the PLLs, SCF clock, etc. A crystal (4 to 18.25 MHz) may be connected as shown, or an external frequency source may be capacitor coupled to Pin 15. See text for crystal requirements.
1) For the MC33411A the Fref Out can be disabled via the MCU interface. 2) For the MC33411B this output is always active (on).
Tx PLL VCC
100 Disable
15 Fref In
17
DS Out (Output)
VCC Audio 100 k
VCC Audio
Data Slicer Output (open collector with internal 100 k pull-up resistor).
17 DS Out
18
Tx Out (Output)
VCC Audio
18, 20
Tx Out is the Tx path audio output. Internally this pin has a low-pass filter circuitry with -3.0 dB bandwidth of 4.0 kHz. Tx gain and mute are programmable through the MCU interface. This pin is sensitive to load capacitance. C Out is the compressor output.
20
C Out (Output) Lim In (Input)
Tx Out, , C Out VB VCC Audio
19
Lim In is the limiter input. This pin is internally biased and has an input impedance of 400 k. Lim In must be ac-coupled.
400 k
19 Lim In
VB
21
Ccap
VCC Audio
VCC Audio 40 k
Ccap is the compressor rectifier filter capacitor pin. It is recommended that an external filter capacitor to VCC audio be used. A practical capacitor range is 0.1 to 1.0 F. The recommended value is 0.47 F.
21 Ccap
NOTE:
1. All VCC pins must be within 0.5 V of each other.
MOTOROLA RF/IF DEVICE DATA
11
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PIN FUNCTION DESCRIPTION (continued)
Description Pin 22 Symbol/Type C In (Input) Description
VCC Audio
MC33411A/B
C In is the compressor input. This pin is internally biased and has an input impedance of 12.5 k. C In must be ac-coupled.
22 C In
12.5 k
VB
23
VCC Audio (Input)
Audio Section, Filters, A/D Converters, Data Slicer
23
10
0.01
VCC
Supply input for the audio section, filters, A/D Converters, and Data Slicer. Allowable range is 2.7 to 5.5 V. Good bypassing is required.
24
MCO (Output)
Audio VCC
Output of the Microphone amplifier. Maximum output swing is 3.0 Vpp for VCC 3.0 V. Maximum output current is >1.0 mA peak.
24 MCO
25
MCI (Input)
VCC Audio
Inverting input of the microphone amplifier. Gain and frequency response are set with external resistors and capacitors from this pin to the audio source and to MCO.
25 MCI VB 2.5 A
26
VAG (Output)
Audio VCC
26 30 k VAG 0.1 F
Analog ground for the audio section filters. VAG is equal to VB and is buffered from VB. Maximum current which can be sourced from this pin is 500 A.
27
VB (Output)
Audio VCC
240 30 k
27 VB 4.7 F
An internal 1.5 V reference for several sections. This voltage is adjustable with bits 3/20-17. Maximum source current is 100 A. PSRR, noise and crosstalk depends on the external capacitor.
28
VCC PA (Input)
Audio Power
28
10
0.01
VCC
Supply pin for the power amplifier outputs. Allowable range is 2.7 to 5.5 V. Good bypassing is required.
NOTE:
1. All VCC pins must be within 0.5 V of each other.
12
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PIN FUNCTION DESCRIPTION (continued)
Description Pin 29 Symbol/Type PAO+ (Output) Description
Audio VCC 29 PAO+
MC33411A/B
Output of the second power amplifier. This amplifier is set for unity inverting gain and is driven by PAO-. Maximum swing is 2.9 Vpp and maximum output current is >5.0 mA peak. DC level is 1.5 V.
30
PAO- (Output) Gnd PA
Same as Pin 29.
Output of the first power amplifier. Its gain is set with external resistors and capacitors from this pin to PAI. Output capability is the same as Pin 28. Ground pin for the power amplifier outputs. A direct connection to a ground plane is strongly recommended. Inverting input of the power amplifier. Gain and frequency response are set with external resistors and capacitors from this pin to the audio source and to PAO-.
31
32
PAI (Input)
VCC Audio
32 PAI
VB 2.5 A
33
E Out (Output)
Audio VCC 33 Rx Audio Output
Expander output. This output is sensitive to load capacitance. Maximum output signal level is 2.5 Vpp. Maximum output current is >1.0 mA.
VB
34
Ecap
VCC Audio 40 k
VCC Audio
34 Ecap
Ecap is the expander rectifier filter capacitor pin. Connect an external filter capacitor between VCC audio and Ecap. The recommended capacitance range is 0.1 to 1.0 F. The suggested value is 0.47 F.
35
E In (Input)
35 E In
VCC Audio
The expander input pin is internally biased and has input impedance of 30 k.
30 k
VB
36
Rx Out (Output)
VCC Audio
Rx Out is the Rx audio output. An internal low-pass filter has a -3.0 dB bandwidth of 4.0 kHz.
36 Rx Out
VB NOTE: 1. All VCC pins must be within 0.5 V of each other.
MOTOROLA RF/IF DEVICE DATA
13
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PIN FUNCTION DESCRIPTION (continued)
Description Pin 37 Symbol/Type RSSI In (Input) Description
VCC Audio
MC33411A/B
Voltage input to RSSI A/D converter. Full scale is 0 to 1.6 V.
37 RSSI In
38
Rx Audio In (Input)
VCC Audio RC Network 38 Rx Audio In VB 600 k
Input to the Rx Audio Path. Input impedance is 600 k. Input signal must be capacitor coupled
39
DS In (Input)
VCC Audio
Input for the digital data from the RF Receiver section. Input impedance is 250 k. Hysteresis is internally provided. Input signal level must be between 50 and 700 mVpp.
250 k
250 k 39 DS In
40
Gnd Audio
Ground pin for the audio section. A direct connection to a ground plan is strongly recommended.
LO2 VCC LO2 VCC 41 LO2 Out 2.5 mA LO2 VCC 50
41
LO2 Out (Output)
Buffered output of the 2nd LO. This high frequency output is a current, requiring an external pullup resistor.
42
LO2 VCC (Input)
LO2 Section
42
10
0.01
10
VCC
Supply pin for the LO2 section. Allowable range is 2.7 to 5.5 V and must be within 0.5 V of all other VCC pins. Good bypassing is required and isolation with a 10 resistor is recommended.
NOTE:
1. All VCC pins must be within 0.5 V of each other.
14
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
PIN FUNCTION DESCRIPTION (continued)
Description Pin Symbol/Type LO2+, LO2- Description 43, 45
LO2 VCC LO2 VCC
MC33411A/B
The 2nd LO. External tank components are required. The internal capacitance across the pins is adjustable from 0 to 7.6 pF for fine tuning performance with bits 7/20-18.
43 LO2+
44
LO2 Ctl (Input)
45 LO2- 44 LO2 Ctl 55 k LO2 VCC
LO2 Control is the dc control input for this VCO. Typically it is the output of the low-pass filter fed from the phase detector output.
46 47
LO2 Gnd LO2PD (Output)
Ground pin for the LO2 section. A direct connection to a ground plane is strongly recommended.
LO2 PLL VCC 100/ 400 A LO2 PLL VCC 100/ 400 A
125 47 to Filter LO2 PD 125
LO2 Phase Detector Output. The output either sources or sinks current, or neither, depending on the phase difference of the phase detector input signals. During lock, very narrow pulses with a frequency equal to the PLL reference frequency are present. Output current is either 100 A or 400 A, selectable with bit 3/14.
48
NOTE:
LO2 Gnd
1. All VCC pins must be within 0.5 V of each other.
Ground pin for the LO2 section. A direct connection to a ground plane is strongly recommended.
MOTOROLA RF/IF DEVICE DATA
15
MC33411A/B
FUNCTIONAL DESCRIPTION
The following text, graphics, tables and schematics are provided to the user as a source of valuable technical information about the MC33411. This information originates from thorough evaluation of the device performance. This data was obtained by using units from typical wafer lots. It is important to note that the forgoing data and information was from a limited number of units. By no means is the user to assume that the data following is a guaranteed parametric. Only the minimum and maximum limits identified in the electrical characteristics tables found earlier in the spec are guaranteed. Note: In the following descriptions, control bits in the MCU Serial Interface for the various functions will be identified by register number and bit number. For example, bit 3/19 indicates bit 19 of register 3. Bits 5/14-11 indicates register 5, bits 14 through 11. Please refer to Figure 1. General Circuit Description The MC33411A/B is a low power baseband IC designed to interface with the MC13145 UHF Wideband Receiver and MC13146 Transmitter for applications up to 2.0 GHz. The devices are primarily designated to be used for 900 MHz ISM band in a CT-900, low power, dual conversion cordless phone, but other applications such as data links with analog processing could be developed. This device contains complete baseband transmit and receive processing sections, a transmit and receive PLL section, a programmable PLL second local oscillator usable to 80 MHz, RSSI and low battery detect circuitry and serial interface for a microprocessor. "A" versions of the device have the ability to disable either the reference oscillator or MCU clock outputs. This feature is useful for systems where the MCU has an internal clock, allowing the user to place the MC33411 into Inactive (lowest power consumption) mode. The "A" version is also useful for systems where the MCU has a dedicated clock source, allowing for lower power consumption from the MC33411 by disabling the MCU clock output. "B" versions of the device are intended for systems where the MCU clock will always be driven from the MC33411. These bits are purposefully "hard-wired" to the enable state to ensure proper operation of the reference oscillator and MCU clock output even during battery discharge/recharge cycles. All internal registers are completely static - no refreshing is required under normal operation conditions. DC Current Figures 2 through 5 are the current consumption for Inactive (MC33411 "A" version only), Standby, Receive, and Active modes versus supply voltages. Figures 6 and 7 show the typical behavior of current consumption in relation to temperature. Figure 8 illustrates the effect of the MCU clock output frequency to supply current during Active mode.
Figure 2. Supply Current versus Supply Voltage (Inactive Mode)
6.0 5.0 SUPPLY CURRENT ( A) 4.0 3.0 2.0 1.0 MCU Clock Off 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 TA = 25C SUPPLY CURRENT (mA) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.0 2.7 3.1
Figure 3. Supply Current versus Supply Voltage (Standby Mode)
TA = 25C
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
16
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
Figure 4. Supply Current versus Supply Voltage (Receive Mode)
10 TA = 25C SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 9.5 MCU Clock Out On 9.0 8.5 MCU Clock Out Off 8.0 7.5 2.7 11 2.7 13 14 TA = 25C MCU Clock Out On
Figure 5. Supply Current versus Supply Voltage (Active Mode)
MCU Clock Out Off 12
3.1
3.5
3.9
4.3
4.7
5.1
5.5
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 6. Supply Current versus Temperature Normalized to 25C (Standby Mode)
740 720 700 I CC, ( A) 680 660 640 620 600 -20 0 25 DEGREES (C) 70 85 VCC = 3.6 V I CC, (mA) 20 19 18 17 16 15 14 13 12 11 10 -20
Figure 7. Supply Current versus Temperature Normalized to 25C (Receive & Active Mode)
Active
VCC = 3.6 V Receive -5.0 10 25 40 55 70 85
DEGREES (C)
Figure 8. Supply Current versus MCU Clock Output Frequency (Active Mode)
12.5 12.3 12.1 11.9 11.7 11.5 30 VCC = 3.6 V TA = 25C
SUPPLY CURRENT (mA)
1030
2030
3030
4030
5030
MCU CLK OUT (kHz)
MOTOROLA RF/IF DEVICE DATA
17
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 1. Tx Gain Adjust Programming (Register 7)
Gain Control Bit #6 Gain Control Bit #5 Gain Ctl # <6 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 >25 Gain Control Bit #9 Gain Control Bit #8 Gain Control Bit #7 Gain/Attenuation Amount -9.0 dB -9.0 dB -8.0 dB -7.0 dB -6.0 dB -5.0 dB -4.0 dB -3.0 dB -2.0 dB -1.0 dB 0 dB 1.0 dB 2.0 dB 3.0 dB 4.0 dB 5.0 dB 6.0 dB 7.0 dB 8.0 dB 9.0 dB 10 dB 10 dB 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 - 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 - 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 - 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 - 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -
MC33411A/B
Transmit Speech Processing System This portion of the audio path goes from "Tx Audio" to "Tx Out". The gain of the microphone amplifier is set with external resistors to receive the audio from the microphone hybrid or any other audio source. The MCO output has rail-to-rail capability. The "Tx Audio" pin will be ac-coupled. The audio transmit signal path includes automatic level control (ALC) (also referred to as the Compressor), Tx mute, limiter, filters, and Tx gain adjust. The ALC provides "soft" limiting to the output signal swing as the input voltage slowly increases. With this technique the gain is slightly lowered to help reduce distortion of the audio signal. The limiter section provides hard limiting due to rapidly changing singal levels, or transients. The ALC, TX mute, and limiter functions can be enabled or disabled vis the MCU serial interface. The Tx gain adjust can also be remotely controlled to set different desired signal levels. The adjustable gain stage provides 20 levels of gain in 1.0 dB increments. It is controlled with bits 7/9-5 as shown in Table 1. The effect of the gain setting under various ALC/Limiter On/Off settings is shown in Figure 9. The Low-Pass Filter before the gain stage is a switched capacitor filter with a corner frequency at 3.7 kHz. This
frequency is dependent upon the SCF clock, nominaly set to 165 kHz and is directly proportional to the SCF clock. The filter response for inband, ripple, wideband, as well as phase and group delay, are shown in Figures 10 through 14. The mute switch at Pin 18 will mute a minimum of 60 dB. Bit 6/2 controls the mute. The limiter can be disabled by programming a logic 1 into 6/5. The compressor with ALC transfer characteristic is shown in Figure 15. The ALC gain is controlled by bits 6/11-12. If both bits are programmed to a logic 0, the ALC gain is set to 5.0 dB. If bit 6/11 is set to a logic 1, the ALC gain will be set to 10 dB, whereas if bit 6/12 is set to a logic 1 the ALC gain will be 25 dB. The ALC function may be disabled by programming a logic 1 into bit 6/6. The compressor low maximum gain can be set with bit 6/8. Programming this bit to a logic 0 sets the maximum gain to 23 dB. A lower maximum gain, nominally 13.5 dB, is achieved by programming the bit to a logic 1. The entire compressor can be bypassed (i.e., 0 dB) by programming bit 6/4 to a logic 1. Figures 16 through 22 describe the characteristics of the compressor, ALC, and limiter.
18
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
Figure 9. Tx Audio Output Voltage versus Gain Control Setting
2.0 0 -2.0 -4.0 -6.0 -8.0 -10 -12 -14 -16 -18 -20 -9.0 VCC = 3.6 V TA = 25C Vin = -10 dBV ALC Off, Limiter Off VOLTAGE GAIN (dB) 5.0 0 -5.0 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 100
Figure 10. Lim In to Tx Out Gain versus Frequency (Inband)
MAX Tx OUT VOLTAGE (dBV)
ALC Off, Limiter On
ALC On, Limiter On/Off
VCC = 3.6 V TA = 25C Vin = -10 dBV 1000 f, FREQUENCY (Hz) 10000
-7.0 -5.0 -3.0 -1.0
1.0
3.0
5.0
7.0
9.0
11
Tx GAIN SETTING (dB)
Figure 11. Lim In to Tx Out Gain versus Frequency (Ripple)
-0.5 -0.6 -0.7 VOLTAGE GAIN (dB) -0.8 -0.9 -1.0 -1.1 -1.2 -1.3 -1.4 -1.5 100 1000 f, FREQUENCY (Hz) 10000 VCC = 3.6 V TA = 25C Vin = -10 dBV 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 100
Figure 12. Lim In to Tx Out Gain versus Frequency (Wideband)
VOLTAGE GAIN (dB)
VCC = 3.6 V TA = 25C Vin = -10 dBV 1000 10000 f, FREQUENCY (Hz) 100000 1000000
Figure 13. Lim In to Tx Out Phase versus Frequency
180 135 90 PHASE (degrees) 45 0 -45 -90 -135 -180 100 1000 f, FREQUENCY (Hz) 10000 0 100 VCC = 3.6 V TA = 25C Vin = -10 dBV 10
Figure 14. Lim In to Tx Out Group Delay versus Frequency
VCC = 3.6 V TA = 25C Vin = -10 dBV 1.0
GROUP DELAY (ms)
0.1
1000 f, FREQUENCY (Hz)
10000
MOTOROLA RF/IF DEVICE DATA
19
MC33411A/B
Figure 15. Compressor Characteristic with Programmable Compressor Maximum Gain
0 Vin > = -4.0 dBV, Vout = 1.26 Vpp (rapidly changing limited signals) Vin = -2.5 dBV, Vout = -10 dBV C OUT VOLTAGE (dBV) -10 C OUT (dBV) "Comp Low Max Gain En" = 0 -20 Maximum Gain = 21 -30 -40 -50 -30 -33 0 -5.0 -10 -15 -20 -25 -30 -35 -40 -60 -50 -40 -30 -20 C IN (dBV) -10 0 -45 -60 -50 -40 -30 -20 2.0 Distortion -10 0 10 0 VCC = 3.6 V TA = 25C R6/8 = 1 Compressor Transfer
Figure 16. Tx Audio Compressor Response (Distortion & Amplitude, ALC off, Lim off)
14 12 10 8.0 6.0 4.0 DISTORTION (%) DISTORTION (%) DISTORTION (%)
-20 Vin = -16 dBV, Vout = -13 dBV (slowly changing ALC signals) "Comp Low Max Gain En" = 1.0 Maximum Gain = 12 -23.5
C IN VOLTAGE (dBV)
Figure 17. Tx Audio Compressor Response (Distortion & Amplitude, ALC off, Lim off)
0 -5.0 C OUT VOLTAGE (dBV) -10 -15 -20 -25 -30 -35 -40 -45 -60 -50 -40 -30 -20 Distortion -10 0 10 2.0 0 VCC = 3.6 V TA = 25C R6/8 = 0 Compressor Transfer 14 12 Tx OUT VOLTAGE (dBV) DISTORTION (%) 10 8.0 6.0 4.0 0 -5.0 -10 -15 -20 -25 -30 -35 -40 -60
Figure 18. Tx Output Audio Response (Lim & ALC off)
4.0 VCC = 3.6 V TA = 25C 3.0
Tx Out
2.0
1.0 Distortion -50 -40 -30 -20 -10 0 0 10
C IN VOLTAGE (dBV)
MCI VOLTAGE (dBV)
Figure 19. Tx Output Audio Response (Lim on, ALC off)
0 -5.0 Tx OUT VOLTAGE (dBV) -10 -15 -20 -25 -30 -35 -40 -60 -50 -40 -30 Distortion -20 -10 0 0 10 1.0 Tx Out 2.0 VCC = 3.6 V TA = 25C 3.0 DISTORTION (%) Tx OUT VOLTAGE (dBV) 4.0 0 -5.0 -10 -15
Figure 20. Tx Output Audio Response (Lim off, ALC on)
4.0 VCC = 3.6 V TA = 25C 3.0 Tx Out -20 -25 -30 -35 -40 -60 -50 -40 Distortion -30 -20 -10 0 0 10 1.0 2.0
MCI VOLTAGE (dBV)
MCI VOLTAGE (dBV)
20
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
Figure 21. Tx Output Audio Response (Lim off, R6/11 = 1)
0 -5.0 Tx OUT VOLTAGE (dBV) -10 -15 -20 -25 -30 -35 -40 -60 -50 -40 -30 Distortion -20 -10 0 0 10 1.0 Tx Out 2.0 VCC = 3.6 V TA = 25C 3.0 DISTORTION (%) Tx OUT VOLTAGE (dBV) 4.0 0 -5.0 -10 -15 -20 -25 -30 -35 -40 -60 -50 -40 Distortion -30 -20 -10 0 0 10 1.0 Tx Out 2.0 VCC = 3.6 V TA = 25C 3.0 DISTORTION (%)
Figure 22. Tx Output Audio Response (Lim off, R6/12 = 1)
4.0
MCI VOLTAGE (dBV)
MCI VOLTAGE (dBV)
Data Slicer The data slicer will receive the low level digital signal from the RF receiver section at Pin 39. The input signal to the data slicer must be >200 mVpp. Hysteresis of 40 mV is internally provided. The output of the data slicer will be same waveform, but with an amplitude of 0 to VCC, and can be observed at Pin 17 if bits 5/9-8 are set to 00. The output can be inverted by setting bit 5/9 = 1. The data slicer can be disabled by setting bit 5/8 = 1. Receive Audio Path The Receive Audio Path (Pins 38, 36-33) consists of an anti-aliasing filter, a low-pass filter, side tone attenuator, gain adjust stage, a mute switch, expander and volume control. The switched capacitor low-pass filter is an 8 pole filter, with a corner frequency at 3.8 kHz. This is designed to provide bandwidth limiting in the audio range.
The gain stage provides 20 dB of gain adjustment in 1.0 dB steps, measured from Pin 38 to 36. Bits 7/4-0 are used to set the gain according to Table 3. The mute switch, controlled by bit 6/1, will mute a minimum of 60 dB. When the compressor output is within 3.0 dB of the expander input level, the Rx output (Pin 36) can be attenuated (referenced to the expander output) by bits 6/10-9. For 6/10-9 = 00, the attenuation is 0 dB. For the other combinations, 6/10-9 = 01, attenuation = 3.0 dB; 6/10-9 = 10, attenuation = 6.0 dB; and 6/10-9 = 11, attenuation = 10.4 dB (See Table 2). The expander can be bypassed by setting bit 6/3 = 1. Table 3 shows the various gain control settings which can be accessed in Register 7. Table 4 is the volume control settings, also located in Register 7. Figures 23 through 31 illustrate the various characteristics of the reveive audio path.
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 2. Side Tone Attenuate Programming
Select # 0 1 2 3 Side Tone Attenuate Bit #1 0 0 1 1 Side Tone Attenuate Bit #0 0 1 0 1 Side Tone Attenuate Amount at Expander Input 0 dB Side Tone Attenuate Amount at Expander Output 0 dB 1.5 dB 3.0 dB 5.2 dB 3.0 dB 6.0 dB 10.4 dB
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 3. Rx Gain Adjust Programming (Register 7)
Gain Control Bit #1 - 1 1 0 0 1 1 0 0 Gain Control Bit #0 - 0 1 0 1 0 1 0 1 Gain Ctl # <6 6 7 8 9 10 11 12 13 Gain Control Bit #4 - 0 0 0 0 0 0 0 0 Gain Control Bit #3 - 0 0 1 1 1 1 1 1 Gain Control Bit #2 - 1 1 0 0 0 0 1 1 Gain/Attenuation Amount -9.0 dB -9.0 dB -8.0 dB -7.0 dB -6.0 dB -5.0 dB -4.0 dB -3.0 dB -2.0 dB
MOTOROLA RF/IF DEVICE DATA
21
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 3. Rx Gain Adjust Programming (Register 7) (continued)
Gain Control Bit #2 1 1 0 0 0 0 1 1 1 1 0 0 - Gain Control Bit #1 1 1 0 0 1 1 0 0 1 1 0 0 - Gain Control Bit #0 0 1 0 1 0 1 0 1 0 1 0 1 - Gain Ctl # 14 15 16 17 18 19 20 21 22 23 24 25 >25 Gain Control Bit #4 0 0 1 1 1 1 1 1 1 1 1 1 - Gain Control Bit #3 1 1 0 0 0 0 0 0 0 0 1 1 - Gain/Attenuation Amount -1.0 dB 0 dB 1.0 dB 2.0 dB 3.0 dB 4.0 dB 5.0 dB 6.0 dB 7.0 dB 8.0 dB 9.0 dB 10 dB 10 dB
MC33411A/B
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 4. Volume Control Programming
Volume Control Bit #11 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Volume Control Bit #10 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Volume Control Bit #13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Volume Control Bit #12 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Volume Ctl # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Gain/Attenuation Amount -14 dB -12 dB -10 dB -8.0 dB -6.0 dB -4.0 dB -2.0 dB 0 dB 2.0 dB 4.0 dB 6.0 dB 8.0 dB 10 dB 12 dB 14 dB 16 dB
22
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
Figure 23. Rx Out Maximum Output Voltage versus Gain Control Setting
2.0 0 -2.0 -4.0 -6.0 -8.0 -10 -12 -14 -16 -18 -20 -9.0 1.4 MAX E OUT VOLTAGE (dBV) VCC = 3.6 V TA = 25C 1.2 1.0 0.8 0.6 0.4 -14 VCC = 3.6 V TA = 25C
Figure 24. E Out Maximum Output Voltage versus Volume Control Setting
MAX Rx OUT VOLTAGE (dBV)
-7.0 -5.0 -3.0 -1.0
1.0
3.0
5.0
7.0
9.0
11
-10
-6.0
-2.0
2.0
6.0
10
14
Rx GAIN SETTING (dB)
VOLUME SETTING (dB)
Figure 25. Rx Audio In to Rx Out Gain versus Frequency (Inband)
5.0 0 -5.0 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 100 0.3 0.2 0.1 VOLTAGE GAIN (dB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 1000 f, FREQUENCY (Hz) 10000 -0.7 100
Figure 26. Rx Audio In to Rx Out Gain versus Frequency (Ripple)
VOLTAGE GAIN (dB)
VCC = 3.6 V TA = 25C Vin = -20 dBV
VCC = 3.6 V TA = 25C Vin = -20 dBV 1000 f, FREQUENCY (Hz) 1000
Figure 27. Rx Audio In to Rx Out Gain versus Frequency (Wideband)
10 0 -10 VOLTAGE GAIN (dB) -20 -30 -40 -50 -60 -70 -80 -90 -100 100 1000 10000 f, FREQUENCY (Hz) 100000 1000000 VCC = 3.6 V TA = 25C Vin = -20 dBV 180 135 90 PHASE (degrees) 45 0 -45 -90 -135 -180 100
Figure 28. Rx Audio In to Rx Out Phase versus Frequency
VCC = 3.6 V TA = 25C Vin = -20 dBV 1000 f, FREQUENCY (Hz) 1000
MOTOROLA RF/IF DEVICE DATA
23
MC33411A/B
Figure 29. Rx Audio In to Rx Out Group Delay versus Frequency
10 VCC = 3.6 V TA = 25C Vin = -20 dBV 10 0 -10 VOLTAGE GAIN (dB) -20 -30 -40 -50 -60 -70 -80 -90 0 100 1000 f, FREQUENCY (Hz) 10000 -100 100 VCC = 3.6 V TA = 25C Vin = -20 dBV SCF Clk = 2.5 MHz SCF Corner = 57 kHz 1000 10000 f, FREQUENCY (Hz) 100000 1000000
Figure 30. AALPF Response Gain versus Frequency
GROUP DELAY (ms)
1.0
0.1
Figure 31. E In to E Out Transfer Curve
5.0 -5.0 E OUT VOLTAGE (dBv) -15 -25 -35 -45 Distortion -55 -65 -40 -35 -30 -25 -20 -15 -10 -5.0 0 4.0 0 Expander Transfer VCC = 3.6 V TA = 25C 28 24 DISTORTION (%) 20 16 12 8.0
E IN VOLTAGE (dBV)
24
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
Power Amplifiers The power amplifiers (Pins 29, 30, 32) are designed to drive the earpiece in a handset, or the telephone line via a hybrid circuit in the base unit. Each output (PAO+ and PAO-) can source and sink 5.0 mA, and can swing 1.3 Vpp each. For high impedance loads, each output can swing 2.7 Vpp (5.4 Vpp differential). The gain of the amplifiers is set with a feedback resistor from Pin 30 to 32, and an input resistor at Pin 32. The differential gain is 2x the resistor ratio. Capacitors Figure 32. Power Amplifier Maximum Output Swing
3.2 2.8 2.4 PAO- (Vpp ) 2.0 1.6 1.2 0.8 0.4 0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 PAI (Vpp) VCC = 3.6 V TA = 25C 0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 Open 130 PAO- (DISTORTION %) 15 20 VCC = 3.6 V TA = 25C 130
can be used for frequency shaping. The pins' dc level is VB (1.5 V). The Mute switch, controlled with bit 6/0, will provide 60 dB of muting with a 50 k feedback resistor. The amount of muting will depend on the value of the feedback resistor. F i g u r e s 32 a n d 33 s h o w t h e p o w e r a m p l i f i e r swing/distortion for VCC = 3.6 V, and Figure 34 illustrates the maximum swing capability for various value of VCC. Figure 33. Power Amplifier Distortion
10
Open
5.0
PAI (Vpp)
3.5 3.0 2.5 PAO- (Vpp ) 2.0 1.5 1.0 0.5 0 2.5
Figure 34. Power Amplifier Maximum Output Swing versus VCC
TA = 25C Open 130
3.0
3.5
4.0 VCC (V)
4.5
5.0
5.5
MOTOROLA RF/IF DEVICE DATA
25
MC33411A/B
a. A programmable 12-bit counter (register bits 4/11-0) to provide the reference frequency for the three PLLs. The 12-bit counter is to be set such that, in conjunction with the programmable counters within each PLL, the proper frequencies can be produced by each VCO. b. A programmable 6-bit counter (register bits 4/17-12), followed by a /2 stage, to set the frequency for the switched capacitor filters to 165 kHz, or as close to that as possible. c. A programmable 3-bit counter (register bits 7/16-14) which provides the MCU clock output (see Tables 5 and 6). A representation of the reference oscillator is given by Figures 35 and 36. Figure 35. Reference Oscillator Schematic
Reference Oscillator
RPI
CPI
Gm
CPO
RPO
Fref In Xtal
Fref Out
C1
C2
26
AA A AAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
Figure 36. Reference Oscillator Input and Output Impedance
Input Impedance (RPI // CPI) 11.6 k // 2.9 pF 4.5 k // 2.5 pF Output Impedance (RPO // CPO)
Reference Oscillator/MCU Clk Out The reference oscillator provides the frequency basis for the three PLLs, the switched capacitor filters, and the MCU clock output. The source for the reference clock can be a crystal in the range of 4.0 to 18.25 MHz connected to Pins 15 & 16, or it can be an external source connected to Fref In (Pin 15). The reference frequency is directed to:
Figures 37 and 38 show a typical gain/phase response of the oscillator. Load capacitance (CL), equivalent series resistance (ESR), and even supply voltage will have an effect on the oscillator response as shown in Figures 39 and 40. It should be noted that optimum performance is achieved when C1 equals C2 (C1/C2 = 1). Figure 41 represents the ESR versus crystal load capacitance for the reference oscillator. This relationship was defined by using a 6.0 dB minimum loop gain margin at 3.6 V. This is considered the minimum gain margin to guarantee oscillator start-up. Oscillator start-up is also significantly affected by the crystal load capacitance selection. In Figure 39, the relationship between crystal load capacitance and ESR can be seen. The lower the load capacitance the better the performance. Given the desired crystal load capacitance, C1 and C2 can be determined from Figure 42. It should also be pointed out that current consumption increases when C1 C2. Be careful not to overdrive the crystal. This could cause a noise problem. An external series resistor on the crystal output can be added to reduce the drive level, if necessary.
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
Figure 37. Reference Oscillator Open Loop Gain versus Frequency
16 14 12 VOLTAGE GAIN (dB) 10 8.0 6.0 4.0 2.0 0 -2.0 -4.0 10.237 10.238
13 pF 13 pF Fref out Fref in 16 15
Figure 38. Reference Oscillator Open Loop Phase versus Frequency
100 80 60 PHASE (degrees) 40 20 0 -20 -40 -60 -80
13 pF 13 pF Fref out Fref in 16 15
VCC = 3.6 V TA = 25C 10.24 MHz, 10 pF Load Capacitance Crystal
VCC = 3.6 V TA = 25C 10.24 MHz, 10 pF Load Capacitance Crystal
10.239
10.240
10.241
10.242
10.243
-100 10.237
10.238
10.239
10.240
10.241
10.242
10.24
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 39. Reference Oscillator Startup Time versus Total ESR - Inactive to Rx Mode
5.0 4.0 START UP TIME (ms) 3.0 2.0 1.0 0 2.048 MHz 5.12 MHz 4.0 0 VCC = 3.6 V TA = 25C GAIN (dB) 20 16 12 8.0
Figure 40. Reference Oscillator Open Loop Gain versus ESR
VCC = 3.6 V TA = 25C
0
50
100
150
200
250
300
350
0
50
100
150
200
250
300
350
TOTAL ESR ()
TOTAL ESR ()
Figure 41. Maximum ESR versus Crystal Load Capacitance (C1 = C2)
1000 70 60 MAXIMUM ESR () 50 C1 AND C2 (pF) 40 30 20 10 10 10 12 14 16 18 20 22 24 26 28 30 32 0 5.0
Figure 42. Optimum Values for C1, C2 versus Equivalent Required Parallel Capacitance
100
10
15
20
25
30
35
CRYSTAL LOAD CAPACITANCE (pF)
CRYSTAL LOAD CAPACITANCE (pF)
MOTOROLA RF/IF DEVICE DATA
27
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 5. MCU Clock Divider Programming
MCU Clk Bit #15 0 0 1 1 0 0 1 1 MCU Clk Bit #16 0 0 0 0 1 1 1 1 MCU Clk Bit #14 0 1 0 1 0 1 0 1 Clk Out Divider Value 2.0 3.0 4.0 5.0 2.5 20 80 312.5
MC33411A/B
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 6. MCU Clock Divider Frequencies
Clock Output Divider 4.0 5.0 Crystal Frequency 10.24 MHz 11.15 MHz 12 MHz 2.0 2.5 3.0 20 80 312.5 5.12 MHz 5.575 MHz 6.0 MHz 4.096 MHz 4.46 MHz 4.8 MHz 3.413 MHz 3.717 MHz 4.0 MHz 2.56 MHz 2.788 MHz 3.0 MHz 2.048 MHz 2.23 MHz 2.4 MHz 512 kHz 557 kHz 600 kHz 128 kHz 139 kHz 150 kHz 32.768 kHz 35.68 kHz 38.4 kHz
Transmit and Receive (LO1) PLL Sections The transmit and receive PLLs (Pins 6-9 and 1-4, respectively) are designed to be part of a 900 MHz system. In a typical application the Transmit PLL section will be set up to generate the transmit frequency, and the Receive PLL section will be set up to generate the LO1 frequency. The two sections are identical, and function independently. External requirements for each include a low-pass filter, a 900 MHz VCO, and a 64/65 or 128/129 dual modulus prescaler. The frequency output of the VCO is to be reduced by the dual modulus prescaler, and then input to the MC33411 (at Pin 8 or 2). That frequency is then further reduced by the programmable 13-bit counter (bits 1/19-7 or 2/19-7), and provided to one side of the Phase Detector, where it is compared with the PLL reference frequency. The output of the phase detector (at Pin 6 or 4) is a Three-State charge pump which drives the VCO through the low-pass filter. Bits 1/20 and 2/20 set the gain of each of the two charge pumps to either 100/2 A/radian or 400/2 A/radian. The polarity of the two phase detector outputs is set with bits 1/21 and 2/21. If the bit = 0, the appropriate PLL is configured to operate with a non-inverting low-pass filter/VCO combination. If the low-pass filter/VCO combination is inverting, the polarity bit should be set to 1. The 7-bit A and A' counters (bits 1/6-0 and 2/6-0) are to be set to drive the Modulus Control input of the 64/65 or 128/129 dual modulus prescalers. The Modulus Control outputs (Pins 9 and 1) can be set to either a voltage mode (logic 1) or a current mode (logic 0) with bit 3/16. To calculate the settings of the N and A registers, the following procedure is used:
f
VCO f PLL
+ Nt (Nt must be an integer)
(1) (2) (3)
Nt P
+N
A = Remainder of Equation 2 (decimal part of N x P)
where: fVCO = the VCO frequency fPLL = the PLL Reference Frequency set within the MC33411 P = the smaller divisor of the dual modulus prescaler (64 for a 64/65 prescaler) N = the whole number portion is the setting for the N (or N') counter within the MC33411 A = the setting for the A (or A') counter within the MC33411 For example, if the VCO is to provide 910 MHz, and the internal PLL reference frequency is 50 kHz, then the equations yield: Nt N A 10 + 910 xx 1036 + 18, 200 50
200 + 18,64 + 284.375
+ 0.375 x 64 + 24
The N register setting is 284 (0 0001 0001 1100), and the A register setting is 24 (001 1000).
28
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
2nd LO (LO2) This PLL is designed to be the 2nd Local Oscillator in a typical 900 MHz system, and is designed for frequencies up to 80 MHz. The VCO and varactor diodes are included, and are to be used with an external tank circuit (Pins 43-45). Bits 4/20-18 are used to select an internal capacitor, with a value in the range of 0 to 7.6 pF, to parallel the varactor diodes and the tank's external capacitor. This permits a certain amount of fine tuning of the oscillator's performance. See Table 7. A buffered output is provided to drive, e.g., a mixer. The frequency is set with the programmable 14-bit counter (bits 3/13-0) in conjunction with the PLL reference frequency. For example, if the reference frequency is 50 kHz, and the 2nd LO frequency is to be 63.3 MHz, the 14-bit counter needs to be set to 1266d (00 0100 1111 0010). The output level is dependent on the value of the impedance at Pin 41, partly determined by the external pull-up resistor. The output of the phase detector is a Three-State charge pump which drives the varactor diodes through an external low-pass filter. Bit 3/14 sets the gain of the charge pump to either 100/2 A/radian (logic 0) or 400/2 A/radian (logic 1). Bit 3/15 sets its polarity - if 0, the PLL is configured to operate with a non-inverting low-pass filter/VCO combination. If the low-pass filter/VCO combination is inverting, the polarity bit should be set to 1. Please note that the 2nd LO VCO on the MC33411 is of the non-inverting type. Figures 43 through 45 describe the response of the 2nd LO.
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 7. LO2 Capacitor Select Programming
LO2 Capacitor Select Bit #18 0 1 0 1 0 1 0 1 LO2 Capacitor Select Bit #20 0 0 0 0 1 1 1 1 LO2 Capacitor Select Bit #19 0 0 1 1 0 0 1 1 Select # 0 1 2 3 4 5 6 7 LO2 Capacitor Select Value 0 pF 1.1 pF 2.2 pF 3.3 pF 4.3 pF 5.4 pF 6.5 pF 7.6 pF
MOTOROLA RF/IF DEVICE DATA
29
MC33411A/B
Figure 43. Varicap Capacitance versus Control Voltage
16 15 14 CAPACITANCE (pF) 13 12 11 10 9.0 8.0 7.0 6.0 0 1 2 3 4 5 6 CONTROL VOLTAGE (V) VCC = 3.6 V TA = 25C MINIMUM OVERALL Q 80 70 60 50 60 MHz 40 30 20 10 0 0 200 400 600 800 1000 1200 COIL INDUCTANCE (nH) 80 MHz 30 MHz VCC = 3.6 V TA = 25C
Figure 44. Minimum Overall Q versus Coil Inductance for LO2
Figure 45. LO2 Amplitude versus Overall Tank Parallel Resistance
35 30 LO AMPLITUDE (dBmV) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 TANK RESISTANCE () VCC = 3.6 V TA = 25C FLO = 63.3 MHz
30
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
Loop Filter Characteristics Let's consider the following discussion on loop filters. The fundamental loop characteristics, such as capture range, loop bandwidth, lock-up time, and transient response are controlled externally by loop filtering. Figure 46 is the general model for a Phase Lock Loop (PLL). Figure 46. PLL Model
fi Phase Detector (Kpd) Filter (Kf) VCO (Ko) fo
pole and a zero around the 0 dB point to guarantee sufficient phase margin in this design (Qp in Figure 48). Figure 48. Bode Plot of Gain and Phase in Open Loop Condition
0 Open Loop Gain A, Open Loop Gain 0 -90
Divider (Kn)
Phase Qp p -180
Where: Kpd = Phase Detector Gain Constant Kf = Loop Filter Transfer Function Ko = VCO Gain Constant Kn = Divide Ratio (N) fi = Input frequency fo = Output frequency fo/N = Feedback frequency divided by N From control theory the loop transfer function can be represented as follows: A The open loop gain including the filter response can be expressed as:
A
+ openloop
K jwK n
K (1 pd o
) jw(R2C2)) jw 1 ) jw R2C1C2 C1)C2 + R2C2
1 1
(4)
+
K
KK pd f o Kn
The two time constants creating the pole and the zero in the Bode plot can now be defined as: T1 R2C1C2 + C1 ) C2 T2 (5)
Open loop gain
Kpd can be either expressed as being 200 A/4 or 800 A/4. More details about performance of different type PLL loops, refer to Motorola application note AN535. The loop filter can take the form of a simple low pass filter. A current output, type 2 filter will be used in this discussion since it has the advantage of improved step response, velocity, and acceleration. The type 2 low pass filter discussed here is represented as follows: Figure 47. Loop Filter with Additional Integrating Element
From Phase Detector R2 C1 C2 To VCO
By substituting equation (5) into (4), it follows:
A
openloop
+
K T1 pd o w 2C1K nT2
K
) jwT2 ) jwT1
(6)
The phase margin (phase + 180) is thus determined by: Qp
+ arctan(wT2)-arctan(wT1)
(7)
At =p, the derivative of the phase margin may be set to zero in order to assure maximum phase margin occurs at p (see also Figure 48). This provides an expression for p: dQ p dw
+0+
From Figure 47, capacitor C1 forms an additional integrator, providing the type 2 response, and filters the discrete current steps from the phase detector output. The function of the additional components R2 and C2 is to create a pole and a zero (together with C1) around the 0 dB point of the open loop gain. This will create sufficient phase margin for stable loop operation. In Figure 48, the open loop gain and the phase is displayed in the form of a Bode plot. Since there are two integrating functions in the loop, originating from the loopfilter and the VCO gain, the open loop gain response follows a second order slope (-40 dB/dec) creating a phase of -180 degrees at the lower and higher frequencies. The filter characteristic needs to be determined such that it is adding a
) (wT2)2 1 ) (wT1)2 w + wp + 1 T2T1
1 T1
T2
-
T1
(8)
(9)
Or rewritten:
+ w 1 T2 2
p tan Qp 2
(10)
By substituting into equation (7), solve for T2:
T2
+
)p 4
wp
(11)
MOTOROLA RF/IF DEVICE DATA
31
MC33411A/B
By choosing a value for p and Qp, T1 and T2 can be calculated. The choice of Qp determines the stability of the loop. In general, choosing a phase margin of 45 degrees is a good choice to start calculations. Choosing lower phase margins will provide somewhat faster lock-times, but also generate higher overshoots on the control line to the VCO. This will present a less stable system. Larger values of phase margin provide a more stable system, but also increase lock-times. The practical range for phase margin is 30 degrees up to 70 degrees. The selection of p is strongly related to the desired lock-time. Since it is quite complicated to accurately calculate lock time, a good first order approach is: T_lock The VCO gain is dependent on the selection of the external inductor and the frequency required. The free running frequency of the VCO is determined by: f
+ 2p 1LC
(16) T
In which L represents the external inductor value and CT represents the total capacitance (including internal capacitance) in parallel with the inductor. The VCO gain can be easily calculated via the internal varicap transfer curve shown in Figure 43. As can be derived from Figure 43, the varicap capacitance changes 2.0 pF over the voltage range from 1.0 V to 3.0 V:
[ w3p
(12)
Equation (12) only provides an order of magnitude for lock time. It does not clearly define what the exact frequency difference is from the desired frequency and it does not show the effect of phase margin. It assumes, however, that the phase detector steps up to the desired control voltage without hesitation. In practice, such step response approach is not really valid. If the two input frequencies are not locked, their phase maybe momentarily zero and force the phase detector into a high impedance mode. Hence, the lock times may be found to be somewhat higher. In general, p should be chosen far below the reference frequency in order for the filter to provide sufficient attenuation at that frequency. In some applications, the reference frequency might represent the spacing between channels. Any feedthrough to the VCO that shows up as a spur might affect adjacent channel rejection. In theory, with the loop in lock, there is no signal coming from the phase detector. But in practice small current pulses and leakage currents will be supplied to both the VCO and the phase detector. The external capacitors may show some leakage, too. Hence, the lower p, the better the reference frequency is filtered, but the longer it takes for the loop to lock. As shown in Figure 48, the open loop gain at p is 1 (or 0 dB), and thus the absolute value of the complex open loop gain as shown in equation (6) solves C1:
DCvar + 2.0 pF 2.0 V
(17)
Combining (16) with (17) the VCO gain can be determined by:
Ko
1 + j2.0V
1 2p LC T
*
2p LC
1
T
) DCvar
2
(18)
Although the basic loopfilter previously described provides adequate performance for most applications, an extra pole may be added for additional reference frequency filtering. Given that the channel spacing is based on the reference frequency, and any feedthrough to the first LO may effect parameters like adjacent channel rejection and intermodulation. Figure 49 shows a loopfilter architecture incorporating an additional pole. Figure 49. Loop Filter with Additional Integrating Element
From Phase Detector R2 To VCO R3
C1
+
K
K T1 pd o w2KnT2
) wpT2 2 1 ) w pT1
2 1
(13)
C1
C2
C3
With C1 known, and equation (5) solve C2 and R2: C2
+ C1 T2 * 1 T1 R2 + T2 C2
(14) (15)
For the additional pole formed by R3 and C3 to be efficient, the cut-off frequency must be much lower than the reference frequency. However, it must also be higher than p in order not to compromise phase margin too much. The following equations were derived in a similar manner as for the basic filter previously described.
32
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
Similarly, it can be shown: K Ko pd + - K w2 (C1 ) C2 ) C3) - w2C1C2C3R2R3 ) 1 ) jwT2 openloop 1 ) jwT1 n
A
(19)
In which: T1
(C1 + C1 )) C2)T2 ) (C1C2)T3 C2 ) C3 * w 2C1T2T3
(20)
T2
+ R2C2
(21)
T3
+ R3C3
2
(22)
From T1 it can be derived that:
C2
+ (T1 ) T2)C3 * C1 T2 ) T3 * T1 ) w T1T2T3 T3 * T1 ) 1)
1
(23)
In analogy with (13), by forcing the loopgain to 1 (0 dB) at p, we obtain:
C1(T1
) T2) ) C2T3 ) C3T2 +
K pd o K nw p 2
K
wpT2 wpT1
2 2 (24)
Solving for C1: 2 2 (25)
(T2
* T1)T3C3 * (T3 * T1)T2C3 ) (T3 * T1)
(T3
K
K T1 pd o w p 2K n
1) 1)
wpT2 wpT1
C1
+
* T1)T2 ) (T3 * T1)T3 *
T2
) T3 * T1 ) wp2T1T2T3 T3
By selecting p via (12), the additional time constant expressed as T3, can be set to: T3 1 + Kwp (26)
The K-factor shown determines how far the additional pole frequency will be separated from p. Selecting too small of a K-factor, the equations may provide negative capacitance or resistor values. Too large of a K-factor may not provide the maximum attenuation. By selecting R3 to be 100 k, C3 becomes known and C1 and C2 can be solved from the equations. By using equations (11) and (10), time constants T2 and T1 can be derived by selecting a phase margin. Finally, R2 follows from T2 and C2. A test circuit with the following components and conditions was constructed with these results: Loop Filter (See Figure 49): C1 = 470 pF R2 = 68 k C2 = 3.9 nF R3 = 270 k C3 = 82 pF
LO2 Tank: Ctotal = 39.3 pF Lext = 150 nH, Q = 50 @ 250 MHz Reference Frequency = 10.24 MHz (unadjusted) R Counter = 205 LO2 Counter = 1266 AC Load = 25 Frequency of LO2 = 63.258 MHz Phase Noise @ 50 kHz offset = -107 dBc Sidebands @ 50 kHz & 100 kHz offsets = -69 dBc Low Battery/ RSSI Voltage Measurement Both the Low Battery (bits 5/23-18) and RSSI (bits 5/17-12) measurement circuits have a 6-bit A/D converter whose value may be read back via the SPI. The A/D's sample their voltages at a frequency equal to the internal SCF clock frequency divided by 128. The Low Battery Measurement A/D senses and divides by 2.5 the supply voltage (at Pin 23). Please note that the minimum Low Battery Detect (LBD) voltage is 2.7 V, since there is no guarantee that the device will operate below this value. The RSSI Measurement senses the voltage at Pin 37.
MOTOROLA RF/IF DEVICE DATA
33
MC33411A/B
These values are compared to the internal reference VB (1.5 V) which is available at Pin 37. The value read back from the LBD A/D will therefor be approximately: 63 (V ) CC [ 2.5(VB)(1.07) (27) VB Voltage Adjust and Characteristics VB has a production tolerance of 8%, and can be adjusted over a 9% range using bits 3/20-17. The adjustment steps will be 1.2% each (See Table 8). If desired, VB can be used to bias external circuitry, as long as the load current on this pin does not exceed 10 A. VB varies by less than 0.5% over supply voltage, referenced to VCC = 3.6 V. The value of the de-coupling capacitor connected from VB to ground affects both the noise and crosstalk from the receive and transmit audio paths, so the value should be chosen with caution. Figures 50 and 51 show this relationship.
N(for LBD)
and for the RSSI N(for RSSI)
[ 63 (RSSIVoltage) (VB)(1.07)
(28)
-110 CROSSTALK (dB) Crosstalk -115 -92
-60 CROSSTALK (dB) -65 -70 -75 -80 -85 -90 VCC = 3.6 V TA = 25C 0.1 1.0 Crosstalk, no load Crosstalk, 130 load
-63 -65 -67 -69 -71 -73 -75 10
-97
-120 VCC = 3.6 V TA = 25C -125 0.01 0.1 1.0
-102
-107 10
-95 0.01
VB CAPACITOR (F)
VB CAPACITOR (F)
34
MOTOROLA RF/IF DEVICE DATA
NOISE LEVEL @ Tx OUT (dBV)
NOISE LEVEL @ E OUT (dBV)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 8. VB Voltage Reference Programming
Vref Adjust Bit #18 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Vref Adjust Bit #17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vref Adjust Bit #20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Vref Adjust Bit #19 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Vref Adjust # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Voltage Reference Adjustment Amount -9.0% -7.8% -6.6% -5.4% -4.2% -3.0% -1.8% -0.6% 0.6% 1.8% 3.0% 4.2% 5.4% 6.6% 7.8% 9.0%
Figure 50. Crosstalk/Noise from C In to E Out versus VB Capacitor
-105 Noise -87 -50 -55
Figure 51. Crosstalk/Noise from E In to Tx Out versus VB Capacitor
-61 Noise
MC33411A/B
MCU Serial Interface The MCU Serial Interface is a 3-wire interface, consisting of a Clock line, an Enable line, and a bi-directional Data line. The interface is always active, i.e., it cannot be powered down as all other sections of the MC33411 are disabled and enabled through this interface. After the device power-up (or whenever a reset condition is required), the MCU should perform the following steps: 1. Initialize the Data line to a high impedance state. 2. Initialize the Clock line to a logic low. 3. Initialize the Enable line to a logic low. 4. Pulse the Clock line a minimum of once (RZ format) while leaving the Enable line continuously low. This places the SPI port into a known condition. 5. Load all registers with their desired initial values. The clock (Return-to-Zero format) must be supplied to the MC33411 at Pin 11 to write or read data, and can be any frequency up to 2.0 MHz. The clock need not be present when data is not being transferred. The Enable line must be low when data is not being transferred. Internally there are 7 data registers, 24-bits each, addressed with 4-bits ranging from $h1 to $h7 (see Tables 9 and 10). Register 5, bits 23-12 are read-only bits, while all other register bits are Read/Write. All unused/unimplemented bits are reserved for Motorola use only. The contents of the 7 registers can be read out at any time. All bits are written in, or read out, on the clock's positive transition. The write and read operations are as follows:
Figure 52. Writing Data to the MC33411
1 2 3 24
Clock Data
4-Bit Address
MSB 24-Bit Data from MCU Latch Address
LSB
Latch Data
Enable
a. Write Operation: - To write data to the MC33411, the following sequence is required (see Figure 52): 6. The Enable line is taken high. 7. Five bits are entered: - The first bit must be a 0 to indicate a Write operation. - The next four bits identify the register address (0001-0111). The MSB is entered first. 8. The Enable line is taken low. At this transition, the address is latched in and decoded. 9. The Enable line is maintained low while the data bits are clocked in. The MSB is entered first, and the LSB last. If 24-bits are written to a register which has less than 24 active bits (e.g., register 6), the unassigned bits are to be 0.
10. After the last bit is entered, the Enable line is to be taken high and then low. The falling edge of this pulse latches in the just entered data. The clock line must be at a logic low and must not transition in either direction during this Enable pulse. 11.The Enable line must then be kept low until the next communication. Note: If less than 24 bits are to be written to a data register, it is not necessary to enter the full 24 bits, as long as they are all lower order bits. For example, if bits 0-6 of a register are to be updated, they can be entered as 7 bits with 7 clock cycles in step 4 above. However, if this procedure is used, a minimum of 4 bits, with 4 clock pulses, must be entered.
MOTOROLA RF/IF DEVICE DATA
35
MC33411A/B
Figure 53. Reading Data from the MC33411
Sets Data Pin to Output 1 2 3 24
Clock Data
4-Bit Address
MSB 24-Bit Data from MC33411 Latch Address and Load Data into Shift Register
LSB Sets Data Pin to Input
Enable
b. Read Operation: - To read the output bits (bits 5/23-12), or the contents of any register, the following sequence is required (see Figure 53): 1. The Enable line is taken high. 2. Five bits are entered: - The first bit must be a 1 to indicate a Read operation. - The next four bits identify the register address (0001-0111). The MSB is entered first. 3. The Enable line is taken low. At this transition, the address is latched in and decoded, and the contents of the selected register is loaded into the 24-bit output shift register. At this point, the Data line (Pin 12) is still an input. 4. While maintaining the Enable line low, the data is read out. The first clock rising edge will change the Data line to an output, and the MSB will be present on this line. 5. The full contents of the register are then read out (MSB first, LSB last) with a total of 24 clock rising edges, including the one in step 4 above. It is recommended that the MCU read the bits after the clock's falling edge. 6. After the last clock pulse, the Enable line is to be taken high and then low. The falling edge of this pulse returns the Data Pin to be an input. The clock line must be at a logic low and must not transition in either direction during this Enable pulse. 7. The Enable line must then be kept low until the next communication. Power Supply/Power Saving Modes The power supply voltage, applied to all VCC pins, can range from 2.7 to 5.5 V. All VCC pins must be within 0.5 V of each other, and each must be bypassed. It is recommended a ground plane be used, and all leads to the MC33411 be as short and direct as possible. To reduce the possibility of device latch-up, it is highly recommended that the Audio, Synthesizer and RF VCC portions of the chip be isolated from the main supply through 10 to 25 resistors (see the Evaluation PCB Schematic, Figure 54). This also provides RF-to-Audio noise isolation. The supply and ground pins are distributed as follows: 1. Pin 23 provides power to the audio section. Pin 40 is the ground pin. 2. Pin 28 provides power to the speaker amplifier section. Pin 31 is the ground pin.
3. Pin 3 provides power to the Rx PLL section. Pin 5 is the ground pin. 4. Pin 7 provides power to the Tx PLL section, and the MCU interface. Pin 5 is the ground pin. 5. Pin 42 provides power to the 2nd LO section. Pins 46 and 48 are the ground pins. 6. Pin 14 is the ground pin for the digital circuitry. Power for the digital circuitry is derived from Pin 23. To conserve power, various sections can be individually disabled by using bits 5/7-0 and 6/7 (setting a bit to 1 disables the section). 1. Reference Oscillator Disable (bit 5/0) - The reference oscillator at Pins 15 and 16 is disabled, thereby denying a clock to the three PLLs and the switched capacitor filters. This function is not available on the "B" version. 2. Tx PLL Disable (bit 5/1) - The 13-bit and 7-bit counters, input buffer, phase detector, and modulus control blocks are disabled. The charge pump output at Pin 6 will be in a Hi-Z state. 3. Rx PLL Disable (bit 5/2) - The 13-bit and 7-bit counters, input buffer, phase detector, and modulus control blocks are disabled. The charge pump output at Pin 4 will be in a Hi-Z state. 4. LO2 PLL Disable (bit 5/3) - The VCO, 14-bit counter, output buffer, and phase detector are disabled. The charge pump output at Pin 47 will be in a Hi-Z state. 5. Power Amplifier Disable (bit 5/4) - The two speaker amplifiers are disabled. Their outputs will go to a high impedance state. 6. Rx Audio Path Disable (bit 5/5) - The anti-aliasing filter, low-pass filter, and variable gain stage are disabled. 7. Tx Audio Path Disable (bit 5/6) - Disables the microphone amplifier and low-pass filter. 8. Low Battery/RSSI Measurement Disable (bit 5/7) - Both 6-bit A/Ds are disabled. 9. Data Slicer Disable (bit 5/8) - The data slicer is disabled and DS Out goes to high impedance. 10. MCU Clock Disable (bit 6/7) - The MCU clock counter is disabled and the MCU Clock Output will be in a Hi-Z state. This function is not available on the "B" version. Note: The 12-bit reference counter is disabled if the three PLLs are disabled (bits 5/1-3 = 1).
36
MOTOROLA RF/IF DEVICE DATA
Table 9. Register Map
Bit 20 MSB MSB FTxMC/ LO2 FRxMC Polarity Mode Select MSB MSB Unused Register Bits ALC Gain ALC Gain = 25 = 10 MCU Clock Divide Select Volume Control Tx Gain Adjust Data Slicer Invert 12-Bit Reference Counter Divide Value 14-Bit 2nd LO Counter Divide Value 6-Bit Switched Capacitor Filter Counter Divide Value 6-Bit RSSI A/D Output 2nd LO PD Cur Sel 13-Bit Rx N' Counter Divide Value LSB MSB 13-Bit Tx N Counter Divide Value LSB MSB 7-Bit Tx A Counter Divide Value 7-Bit Rx A' Counter Divide Value Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 0 LSB LSB LSB LSB
Reg Add
Reg Num
MSB Bit 23
Bit 22
Bit 21
0001
1
0010 VB Voltage Reference Adjust LO2 Capacitor Select
2
Tx Tx Polarity Cur PD Sel Select Rx Rx Polarity Cur PD Sel Select
0011
3
0100
4
Test Modes
MOTOROLA RF/IF DEVICE DATA
Data Slicer Disable Comp. Side Tone Attenuate Select Low Max. Gain En. Rx Gain Adjust
0101
5
6-Bit Battery Voltage A/D Output
0110
6
RSSI & Power 2nd LO Rx PLL Tx PLL Ref Osc Batt. A/D Tx Audio Rx Audio Amp PLL Disable Disable Disable Disable Disable Disable Disable Disable* Compres- Expander Power MCU Clk ALC Limiter Pass- Amp Disable* Disable Disable ser Pass- through Tx Mute Rx Mute Mute through
0111
7
* These bits not included in "B" version.
Table 10. Register Map: Power-Up Defaults
Bit 20 MSB 1 MSB 1 MSB 1 0 0 MSB 0 0 0 1 0 0 0 0 0 0 13-Bit Rx N' Counter Divide Value 0 0 0 0 0 0 0 0 0 0 0 0 0 13-Bit Tx N Counter Divide Value 0 0 0 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 LSB 0 LSB 0
Table 9. Register Map
Table 10. Register Map: Power-Up Defaults
MC33411A/B
Reg Add
Reg Num
MSB Bit 23
Bit 22
Bit 21
Bit 6
Bit 5 MSB 1 MSB 1 0 14-Bit 2nd LO Counter Divide Value 0 0 0 0 0
Bit 4
Bit 3
Bit 2
Bit 1 7-Bit Tx A Counter Divide Value 0 0 0 7-Bit Rx A' Counter Divide Value 0 0 0 0 0
LSB Bit 0 LSB 0 LSB 0 LSB 0 12-Bit Reference Counter Divide Value 0 0 0 0 LSB
0001
1
0010
2
Tx Tx Polarity Cur PD Sel Select 0 0 Rx Rx Polarity Cur PD Sel Select 0 0 VB Voltage Reference Adjust 0 LO2 Capacitor Select 0 0 0 1 0 0 1 1 1 0 0 FTxMC/ LO2 FRxMC Polarity Mode Select 0 0 0 2nd LO PD Cur Sel 0
0011
3
0100
4
Test Modes
6-Bit Switched Capacitor Filter Counter Divide Value
0
0
0
0101
5
6-Bit Battery Voltage A/D Output
6-Bit RSSI A/D Output
Unused Register Bits 0 0 ALC Gain ALC Gain = 25 = 10 0 0
0 Data Slicer Invert 0
0110
6
0 Data Slicer Disable 0 Comp. Side Tone Attenuate Select Low Max. Gain En. 0 0 0 MCU Clock Divide Select 0 1 1 0 Volume Control 1 1 1 0 1
0 0 0 0 0 0 0 0 RSSI & Tx Audio Rx Audio Power 2nd LO Rx PLL Tx PLL Ref Osc Batt. A/D Disable Disable Amp PLL Disable Disable Disable Disable Disable Disable* 0 0 0 0 0 0 0 0 MCU Clk ALC Limiter Compres- Expander Tx Mute Rx Mute Power Pass- Amp Disable* Disable Disable ser Pass- through through Mute 0 0 0 0 0 0 0 0 Tx Gain Adjust 1 1 1 0 1 Rx Gain Adjust 1 1 1
0111
7
37
* These bits not included in "B" version.
MC33411A/B
Evaluation PCB The evaluation PCB is a versatile board which allows the MC33411 to be configured to analyze individual operating parameters or the complete audio transmit and receive paths. The general purpose schematic and associated parts list for the PCB are given in Figure 54. With the jumpers positioned as shown in the parts list (either shunt or open). the PCB is configured to analyze complete transmit and receive audio paths. Parts lists as "user defined" can be installed to analyze other functions of the device. Table 11 lists these devices along with their respective functions.
Table 11. Component(s)
R20 R19,J24,J27 R3,C7,J5 R4,C8 L1,C21 C18,R9,C19,R10,C20 C26,R13,C27,R14,C28 C22,R11,C23,R12,C24
Function
Microphone Bias Pre-emphasis/De-emphasis Detector Low-Pass Filter (LPF) Data Slicer LPF 2nd LO Tank 2nd LO LPF Rx 1st LO LPF Tx 1st LO LPF
Notes
See Equations 16 and 17 See Eq. 10, 11, 12, 21, 23, 25, and 26 See Eq. 10, 11, 12, 21, 23, 25, and 26 See Eq. 10, 11, 12, 21, 23, 25, and 26
38
MOTOROLA RF/IF DEVICE DATA
R9 U/D C18 U/D
V CCR C29 0.01 C25 0.01
VCCD
AAAA AAAA
MOTOROLA RF/IF DEVICE DATA 39
Figure 54. MC33411A/B Evaluation PCB Schematic
R6 J27 N/O J25 N/C J26 N/C PA In TP4 E In TP3 47.5 k C13 220 p R5 47.5 k
R7 130 J8 N/O C12 1.0 V CCA C10 1.0 J6 N/C R1 47.5 k J23 N/C J7 N/C C12 1.0 C38 4.7 C39 0.1 R19 U/D V CCA C1 1.0 J24 N/O C In TP1 R2 47.5 k C2 220 p J2 N/C C3 1.0 C4 0.47 U/D Tx AUD J1 R20 PA Out- J10 PA Out+ J9
Figure 54.
V CCA
AUD In J4
V CCL J5 N/O R3 U/D C7 U/D R4 U/D C8 U/D R18 49.9 C14 0.01 C6 1.0 C9 1.0 C40 0.01 37 RSSI In 38 Rx Audio In 39 DS In 40 Gnd Audio 41 LO2 Out 42 LO2 V CC 43 LO2+ 44 LO2 Ctl 45 46 47 48 LO2- LO2 Gnd LO2 PD LO2 Gnd R x O u t
3 6
333 3332 543 2109 EEEPGPP AnAA I cOI dOO nau pt P-+ A
22 65 VVVM CBAC C GI P A
2 8
2 7
LO2 Out J16 L1 U/D C21 U/D
V CCL
U1 MC33411
Mic Amp 24 VCC Audio 23 C In 22 C cap 21 C Out 20 Lim In 19 Tx Out 18 DS Out 17
V CCA Lim In TP2
MC33411A/B
TP6 C5 1.0 J3 N/C VCCD J17 C15 27 p Y1 10 M C16 27 p R8 49.9 Gnd J18 TP7 C30 10
D1 1N4001 C31 0.01
R15 10 C32 10 R16 10 C34 10 R17 10
V CCA C33 0.01
LO2 Ctl TP5 C20 U/D R10 U/D C19 U/D J15 N/C
P L F L R xFV MRC CxC 1
R x P D
P L L G n d
T x P D
P L F L T D Ca VFx CTMEL t CxCNKa 11 01
Fref Out 16 Fref In 15 Gnd Digital 14 MCU Clk Out 13
J11 N/C J12 N/C J13 N/O C17 0.01
V CCR C35 0.01
234
56789
1 2
JP1
1 2 3 4 5 6 7 8 9 10
F In J14
C36 10
V CCL C37 0.01
C26 U/D JP3
1 2 3 4 5 6 7 8 9 10 Det In RSSI RX EN Rx PD Rx MC FRx
C22 U/D R11 U/D R12 U/D C23 U/D C24 U/D
C27 U/D C28 U/D
R13 U/D R14 U/D
Tx DAT Tx EN Rx EN EN CLK Data CK Out DS Out
H5X2 JP2
1 2 3 4 5 6 7 8 9 10
FTx
Tx MC Tx PD Tx EN
H5X2
Tx Out Tx DAT
H5X2
MC33411A/B
Figure 55. MC33411A/B Evaluation PCB Component Side
4.5
4.5
C1,C3,C5,C6,C9,C10,C12 C13,C2 C4,C11 L1,R3,R4,C7,C8,R9,R10, R11,R12,R13,R14,C18,R19, C19,R20,C20,C21,C22,C23, C24,C26,C27,C28 C14,C17,C25,C29,C31,C33, C35,C37,C40 C15,C16 C30,C32,C34,C36 C38 C39 D1
1.0 220 p 0.47 User defined
JP1,JP2,JP3 J1,J4,J9,J10 J2,J3,J6,J7,J11,J12,J15, J23,J25,J26 J5,J8,J13,J24,J27 J14,J16 J17,J18 R1,R2,R5,R6 R7 R8,R18 R15,R16,R17 U1 Y1
Header, 5x2 AudioJack Switchcroft 3501FP Shunt Open SMA EF Johnson 142-0701-201 Bananna Johnson Components 108-0902-001 47.5 k 130 49.9 10 MC33411AFTA or MC33411BFTA 10 M Raltron A-10.000-18
0.01 27 p 10 4.7 0.1 1N4001
Default Units: Microfarads, Microhenries, and Ohms
40
MOTOROLA RF/IF DEVICE DATA
MC33411A/B
Figure 56. MC33411A/B Evaluation PCB Solder Side
4.5
4.5
MOTOROLA RF/IF DEVICE DATA
41
MC33411A/B
OUTLINE DIMENSIONS
FTA SUFFIX PLASTIC PACKAGE CASE 932-02 (LQFP-48) ISSUE E
4X NOTES: 1 DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9 EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 1_ 5_ 12 _REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
0.200 AB T-U Z 9 A1
48 37
A
DETAIL Y
P
1
36
T B B1
12 25
U V AE V1 AE
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-U Z
AB
G
0.080 AC
AD AC
BASE METAL
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
M_
TOP & BOTTOM
R
GAUGE PLANE
0.080
SECTION AE-AE
42
CCC EEE CCC EEE CCC
F D
M
C
E
AC T-U Z H DETAIL AD AA W K L_
MOTOROLA RF/IF DEVICE DATA
0.250
N
J
MC33411A/B
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. - http://sps.motorola.com/mfax/ 852-26668334 HOME PAGE: http://motorola.com/sps/ JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
MOTOROLA RF/IF DEVICE DATA
MC33411A/D 43

▲Up To Search▲

Price & Availability of MC33411B

	To Download MC33411B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .